The present invention relates to a power consumption reduced register circuit and in particular to a power consumption reduced register circuit in which power consumption is reduced by controlling clock signals which are input to registers of a data processing circuit for signal processing in response to changes in data which are input to each register.
Large scale integrated circuits include various functional circuit blocks such as flip-flops which accept data input signals input thereto in synchronization with clock signals. If synchronous circuits are dealt in designing of LSIs, functional blocks such as flip-flop circuits are designed in such a manner that clock signals are constantly input thereto.
As the scale of LSIs is increased and the operational speed becomes higher, a larger number of flip-flop circuits are incorporated in a LSI chip and clock signals are constantly input to the flip-flop circuits even if it is not necessary to change the states of the flip-flop circuits. Accordingly, there is a problem that unnecessary power is consumed due to the fact that the clock signals are input even if changes in the states of the flip-flop circuits are not necessary. There is the need to suppress such unnecessary change in clock signal.
In order to overcome the above-mentioned problem, Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 7-99434 entitled "Power consumption reduced circuit" proposes a power consumption reduced circuit having functional circuit blocks for accepting data input signals supplied thereto in synchronization with clock signals, comprising a first circuit means for determining whether or not it is necessary for the function blocks to perform an accepting operation of the data input signals, and a second circuit means for permitting the clock signal to be output when the first circuit means outputs a signal representing that the signal accepting operation is necessary and for prohibiting the clock signal to be output when the first circuit means outputs a signal representing that the signal accepting operation is not necessary, whereby a clock signal output from the second circuit means is supplied as the clock signal for the functional circuit blocks.
FIG. 1 is a view for explaining the power consumption reduced circuit which is disclosed in Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 7-99434. In the drawing, functional blocks of part of an LSI are shown. When an initiating signal l.sub.1 is input, this initiating signal l.sub.1 is received by a first-stage circuit unit 6 and a flip-flop 1 to which clock signals are constantly supplied. The first-stage circuit unit 6 activates the operation of the whole of the circuit shown in FIG. 1 and the flip-flop 1 triggers a flip-flop 2 via an OR gate 4.
The flip-flop 2 self-holds its state by feeding-back a signal l.sub.4 from an output terminal of the flip-flop 2 by means of a self-holding operating circuit comprising an AND gate 3 and OR gate 4 and when an output signal l.sub.5 of a NOR gate 8 assumes "1" the feed-back loop is cut off so that the flip-flop 2 is reset. A NOR gate 8 determines whether or not a subsequent circuit unit 7 is in operation, that is, it is necessary to change the self-need state by accepting the data input signal. In operation, the NOR gate 8 provides a result of signals representing necessity of accepting the data input signals.
Registers 9 (register A), 11 (register B), 13 (register C) and 15 (register D) are configured so that their latch timing control is conducted in response to a signal generated from the first-stage circuit unit 6 or the subsequent stage circuit unit 7 if necessary. Logical circuits 10 (logical circuit A), 12 (logical circuit B) and 14 (logical circuit C) are circuits for logically combining the outputs of the registers (A)9, (B)11, (C)13 and (D)15. The circuits may configured in any manner.
FIG. 2 is a timing chart explaining the operation in FIG. 1. A reference numeral l.sub.2 denotes an input clock signal; l.sub.1 the initiating signal; l.sub.3 an output signal of the flip-flop 1, l.sub.4 an output signal of the flip-flop 2, l.sub.5 and output signal of the NOR gate 8, and l.sub.6 output signal of the AND gate 5 (internal clock). The internal clock l.sub.6 which is an output of the AND gate 5 serves as a gated clock and is applied to the subsequent circuit unit 7 and the registers 11 and 13.
The clock signals which are applied to a unit in which a unit for performing a closed operation for the functional blocks (for examples, a logic for determining the change of a flip-flop including a register) exists only in the functional blocks are generated only in a period of time when the functional blocks are operated. Normal clock signals are applied to the flip-flops which are capable of determining the change in response to an input signal from the other functional blocks. Clocks are necessary as timing information to cause storing elements of the functional blocks such as flip-flops, registers, memories and the like to operate only when they operate to change their states. Clocks are not necessary when the storing elements are not operated.
In case of D type flip-flop, a circuit comprising a three-input AND equivalent element is coupled to a clock input signal as mentioned above. Since it performs repeatingly assumes "1" or "0" in synchronization with the clock inputs, power is consumed in this unit. Reduction in power consumption can be achieved in a functional block having less frequency of operations, in particular a CMOS circuit if unnecessary clocks are provided. When a reset signal l.sub.7 is used, it is necessary to turn the flip-flop 2 on in order that a reset operation will be normally completed.
In the invention as defined in Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 7-99434, reduction in power consumption is achieved by suppressing the changes in unnecessary clock signals, that is, by prohibiting the application of the clock signals to the registers (B)9 and (C)7 when the same data is input. However, it is necessary that respective outputs of the registers A, B, C and D correspond to the outputs of the registers, which are desired to obtain in respective stages in a four-stage pipeline configured structure on a one-to-one basis as shown in a lower column of FIG. 3 (clock control method of the present invention) if the data inputs and outputs of the four-stage pipe line configured circuit is considered (hatching represents identical data in FIG. 3).
However, disturbance of the pipeline is caused in the configuration as set forth in Japanese Laid-Open Patent Publication (TOKKAIHEI) No. 7-99434 as shown in the upper column in FIG. 3 (prior art clock control method) so that one-to-one correspondence between the respective outputs of the registers A, B, C and D and their output can not be kept. That is, there is a problem that the output of the register D in the final stage does not correspond to its input since the same clock signal is applied to the registers B and C.